1. Field of the Invention
The present invention relates to the field of processors; more specifically, the present invention relates to an instruction buffer circuit for buffering multiple instructions for a processor simultaneously and a method of buffering multiple instructions for a processor simultaneously.
2. Background of the Invention
In a high performance processor application in order to maximize the number of instructions executed concurrently and to provide high bandwidth to the instruction cache, a large register file instruction buffer (IBUF) supporting multiple writes and reads is required. In our application, a 64-entry instruction buffer supporting 8 concurrent writes and 5 concurrent reads is required to allow for high concurrency in the pipeline. The conventional approach is to implement the register file instruction buffer with 8 write ports and 5 read ports. This approach requires a large SRAM cell area to support the required numerous read and write ports. It also requires a complex decoding scheme resulting in a slow access and large array area. The multi-ported array therefore represents a potential integration and timing problem. Therefore, an instruction buffer capable of supporting multiple writes and multiple reads concurrently and requiring a minimum amount of memory area and fast access is needed.